The present disclosure relates to semiconductor devices. As recent memory devices have been highly integrated and downsized, the size of active regions has been also reduced in a semiconductor substrate. Thus, the gate resistance and the threshold voltage may increase due to the decrease of the gate width and the channel length in cell transistors. Particularly, the decrease of the channel length in a metal oxide semiconductor field effect transistor (MOSFET) may cause the deterioration of gate channel characteristics, which is a phenomenon known as a short channel effect.
In addition, the size reduction of the active region may increase proximity between the gate electrode and the source junction and between the gate electrode and the drain junction, thus generating an excessive electric field between the gate electrode and the source/drain junctions that may cause a gate-induced drain leakage (GIDL). Further, the gate current may pass toward the source/drain junctions, which is a phenomenon known as current leakage.
Accordingly, the size reduction of semiconductor devices has brought about various technologies for addressing the short channel effect and current leakage. For example, it has been suggested to provide a fin gate structure in which the gate electrode protrudes into a fin shape and to expand the channel, or to provide a gate-all-around (GAA) structure in which the channel is enclosed by the gate electrode, or to provide a multichannel structure in which a single gate electrode contacts a plurality of the channels, or to provide various vertical transistors including one of the above fin gate structures, GAA structures, or multichannel structures. Moreover, a nano wire channel transistor has been suggested for high performance with a low power. In a nano wire channel transistor, the channel of the GAA structure is replaced with a nano wire channel.
However, the size reduction of semiconductor devices may increase parasitic capacitance and electrical resistance as well as the short channel effect and current leakage, so that a vertical transistor may benefit from decreasing the parasitic capacitance and the electrical resistance for a stable operation. Particularly, when the line width of the gate electrode is decreased to a few/several nanometers, the width of the gate spacer also decreases and as a result, the parasitic capacitance may become very high between the gate electrode and the adjacent contact. In addition, the width reduction of the gate electrode and the contact may increase the electrical resistance of the gate electrode and the contact.